Computer Organization and Architecture - B.Tech 4th Semester Exam., 2022 (New Course)

2022•Semester 3•Civil-CA•End Semester
Bihar Engineering University, Patna
B.Tech 4th Semester Exam., 2022 (New Course)

Computer Organization and Architecture

Time: 3 hoursCode: 105401/106401Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Choose the correct answer of the following (any seven) :[2x7=14]

  1. The 8-bit encoding format used to store data in a computer is

    1. ASCII
    2. EBCDIC
    3. ANCI
    4. USCII

  2. The bus used to connect the monitor to the CPU is

    1. PCI bus
    2. SCSI bus
    3. memory bus
    4. ram bus

  3. The alternate way of writing the instruction, ADD #5, R1 is

    1. ADD [5],[R1];
    2. ADDI 5,R1;
    3. ADDIME 5, [R1];
    4. There is no other way

  4. The instruction fetch phase ends with

    1. placing the data from the address in MAR into MDR
    2. placing the address of the data into MAR
    3. completing the execution of the data and placing its storage address into MAR
    4. decoding the data in MDR and placing it in IR

  5. For converting a virtual address into the physical address, the programs are divided into

    1. pages
    2. frames
    3. segments
    4. blocks

  6. The transfer of large chunks of data with the involvement of the processor is done by

    1. DMA controller
    2. arbitrator
    3. user system programs
    4. None of the above

  7. The computer architecture aimed at reducing the time of execution of instructions is

    1. CISC
    2. RISC
    3. ISA
    4. ANNA

  8. Which table handle stores the addresses of the interrupt handling sub-routines?

    1. Interrupt-vector table
    2. Vector table
    3. Symbol link table
    4. None of the above

  9. The situation wherein the data of operands are not available is called

    1. data hazard
    2. stock
    3. deadlock
    4. structural hazard

  10. The DMA controller has ___ registers.

    1. 4
    2. 2
    3. 3
    4. 1
Q.2 Solve both questions :[7+7=14]

  1. List and briefly define the main structural components of a computer.

  2. Discuss the design and logic of a microprogram sequence.

Q.3 Solve all questions :[14]

  1. Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields the first contains the opcode and the remainder the immediate operand or an operand address.
    What is the maximum directly addressable memory capacity (in bytes)?

    Discuss the impact on the system speed if the microprocessor bus has (i) a 32-bit local address bus and a 16-bit local data bus, or (ii) a 16-bit local address bus and a 16-bit local data bus.

    How many bits are needed for the program counter and the instruction register?

Q.4 Solve both questions :[7+7=14]

  1. A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor's addresses are interpreted.

  2. Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

Q.5 Solve both questions :[7+7=14]

  1. Calculate (72530-13250) using ten's complement arithmetic. Assume rules similar to those for two's complement arithmetic.

  2. List and briefly explain five important instruction set design issues.

Q.6 Solve this question :[14]

  1. The x86 architecture includes an instruction called decimal adjust after addition (DAA). DAA performs the following sequence of instructions :
    if((AL AND OFH)>9) OR \( (AF=1) \) then \( AL \leftarrow AL+6 \); AF 1; else AF 0; endif;
    if (AL> 9FH) OR \( (CF=1) \) then \( AL \leftarrow AL+60H \); CF-1; else CF 0; endif.
    "H" indicates hexadecimal. AL is an 8-bit register that holds the result of addition of two unsigned 8-bit integers. AF is a flag set if there is a carry from bit 3 to bit 4 in the result of an addition. CF is a flag set if there is a carry from bit 7 to bit 8. Explain the function performed by the DAA instruction.

Q.7 Solve both questions :[14]

  1. A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI (cycles per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
    1. What is the speedup achieved for a typical program?
    2. What is the MIPS rate for each processor?

Q.8 Solve both questions :[7+7=14]

  1. Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines.

  2. A computer has 16 registers, an ALU with 32 operations, and a shifter with 8 operations, all connected to a common bus system. (i) Formulate a control word for micro-operation. (ii) Show the bits of the control word that specify the micro-operation \( R4 \leftarrow R5+R6 \).

Q.9 Solve this question :[14]

  1. Let a be the percentage of a program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of x MIPS.
    Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program, in terms of n, a and x.

    If \( n=16 \) and \( x=4 \) MIPS, determine the value of that will yield a system performance of 40 MIPS.