Computer Organization & Architecture - B.Tech 4th Semester Examination, 2024

2024•Semester 3•Civil-CA•End Semester
Bihar Engineering University, Patna
B.Tech 4th Semester Examination, 2024

Computer Organization & Architecture

Time: 03 HoursCode: 105401Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Choose the correct answer of the following (any seven question only):[2x7=14]

  1. What is the first step in the instruction execution cycle?

    1. Decode
    2. Execute
    3. Fetch
    4. Store

  2. What is the advantage of carry look-ahead adders over ripple carry adders?

    1. Simplicity in design
    2. Increased latency
    3. Reduced power consumption
    4. Faster addition by reducing carry propagation delay

  3. Which type of control unit is faster but more difficult to modify?

    1. Hardwired Control Unit
    2. Microprogrammed Control Unit
    3. Cache Control Unit
    4. Memory Management Unit

  4. Which of the following I/O transfer methods involves the CPU polling the device until data is ready?

    1. DMA
    2. Interrupt-driven I/O
    3. Program-controlled I/O
    4. Asynchronous I/O

  5. What does a branch prediction mechanism in a CPU help reduce?

    1. Data hazards
    2. Structural hazards
    3. Control hazards
    4. Clock cycle delays

  6. Which of the following is NOT a type of parallel processor architecture?

    1. SIMD
    2. MIMD
    3. SISO
    4. Multi-core

  7. Which cache replacement algorithm removes the least recently used block?

    1. FIFO
    2. LFU
    3. LRU
    4. Random Replacement

  8. Which technique is used to handle data hazards in pipelining?

    1. Increasing memory size
    2. Instruction scheduling
    3. Parallel processing
    4. Increasing clock speed

  9. Which addressing mode directly specifies the operand within the instruction?

    1. Direct Addressing
    2. Immediate Addressing
    3. Indirect Addressing
    4. Indexed Addressing

  10. A computer with 32 bit wide data bus uses \( 1K \times 8 \) static RAM memory chips. What is smallest memory that this computer have?

    1. 32K
    2. 8K
    3. 16K
    4. 24K
Q.2 Solve both questions :[7+7=14]

  1. Describe the instruction execution cycle in a CPU. Explain some key features of the x86 architecture.

  2. Explain different addressing modes in a CPU with an examples.

Q.3 Solve both questions :[7+7=14]

  1. Explain the Addition and Subtraction Algorithm with the help of flowchart.

  2. What is a Carry-look ahead fast adder? Draw the circuit of an 8-bit carry-look ahead adder using 4-bit carry look ahead adder.

Q.4 Solve both questions :[7+7=14]

  1. Explain different cache replacement algorithms used in memory management.

  2. What are the different types of Registers? With the diagram show how the basic computer register connected to a common Bus.

Q.5 Solve both questions :[7+7=14]

  1. Illustrate what are the challenges associated with concurrent access to memory in parallel processing?

  2. Describe different cache coherence protocols used in parallel processors.

Q.6 Solve both questions :[7+7=14]

  1. A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determine the speedup ratio of the pipeline for 100 task.

  2. What are pipeline hazards? Explain different types of hazards in pipelining.

Q.7 Solve this question :[14]

  1. Explain Booth's algorithm for multiplication with the help of flowchart. Provide an example for its implementation.

Q.8 Solve this question :[14]

  1. Describe different types of Input/Output transfers. Explain how data transfer take place through DMA.

Q.9 Write short notes on any two of the following:-[7x2=14]
    • RISC and CISC processor
    • I/O device interfaces
    • fixed and floating point representations
    • Instruction Set Architecture