Digital Electronics - B.Tech 3rd Semester Exam., 2020

2020•Semester 2•Civil-CA•End Semester
Bihar Engineering University, Patna
B.Tech 3rd Semester Exam., 2020

Digital Electronics

Time: 03 HoursCode: 100305Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Choose the correct answer of the following (any seven):[14]

  1. Dynamic RAM employs

    1. capacitor or MOSFET
    2. FET or JFET
    3. capacitor or BJT
    4. BJT or MOS

  2. The resolution of a 10-bit AD converter for an input range of 10 V is approximately

    1. 1 V
    2. 1 mV
    3. 10 mV
    4. 100 mV

  3. The evolution of PLD begins with

    1. EROM
    2. RAM
    3. PROM
    4. EEPROM

  4. The parameter through which 16 distinct values can be represented is known as

    1. bit
    2. byte
    3. word
    4. nibble

  5. The number of full and half adders required to add 16-bit number is

    1. 8 HA, 8 FA
    2. 1 HA, 15 FA
    3. 16 HA, 0 FA
    4. 4 HA, 12 FA

  6. If we record any music in any recorder, such type of process is called

    1. multiplexing
    2. encoding
    3. decoding
    4. demultiplexing

  7. The no. of D flip-flop required to form a 5-bit ring counter is

    1. 3
    2. 4
    3. 5
    4. None of the above

  8. An overflow is a/an

    1. hardware problem
    2. software problem
    3. user-input problem
    4. input-output problem

  9. The systematic reduction of logic circuits is accomplished by

    1. symbolic reduction
    2. TTL logic
    3. Boolean algebra
    4. truth table

  10. A latch is an example of a/an

    1. monostable multivibrator
    2. astable multivibrator
    3. bistable multivibrator
    4. 555 timer
Q.2 Solve both questions :[8+6=14]

  1. (a) Design an excess-3 to BCD code converter using minimum number of NAND gates.

  2. (b) Prove the following:
    \( A \oplus B = \overline{A} \oplus \overline{B} \)
    \( A \oplus \overline{B} = \overline{A \oplus B} = \overline{A} \oplus B \)

Q.3 Solve both questions :[6+8=14]

  1. (a) How can we implement preset and clear inputs in a flip-flop? Explain with the help of a diagram and list their uses.

  2. (b) Design a Mod 9 counter using T flip-flops.

Q.4 Solve both questions :[6+8=14]

  1. (a) Explain internal organization of \( 16 \times 2 \) memory chips using suitable diagrams. Calculate the maximum rate at which data can be stored and read for a memory having following timing parameters:

    Parameter Time (ns)
    Read to Output Valid Time \( (t_{RD}) \) 70
    Data Setup Time \( (t_{DW}) \) 120
    Read to Cycle Time \( (t_{RC}) \) 200
    Write Release Time \( (t_{WR}) \) 0
    Write Cycle \( (t_{WC}) \) 200

  2. (b) Differentiate between Word Capacity and Word Size. Design a \( 16 \times 8 \) CAM, using \( 8 \times 2 \) CAM chips.

Q.5 Solve both questions :[6+8=14]

  1. (a) Define resolution, linearity, accuracy and settling time of D/A converters. A typical D/A converter has a full-scale analog output of 10 V and accepts 6 binary bits as input. What will be the voltage corresponding to each analog step?

  2. (b) Design a 3-bit parallel comparator A/D converter that provides output in 2's complement format.

Q.6 Solve both questions :[8+6=14]

  1. (a) Design a BCD to 7-segment display decoder circuit using logic gates.

  2. (b) Design full adder using the following: (i) 8:1 mux (ii) 4:1 mux

Q.7 Solve both questions :[6+8=14]

  1. (a) On the following graph, inputs CLK and D are shown: . They are inputs to a D latch and a positive edge triggered D flip-flop. Assuming initial output 0, draw the output waveform for flip-flop and latch. Do the two outputs differ? If so, why?

    Question Diagram

  2. (b) Explain SIPO and SISO operations of shift register with relevant logic diagrams and truth tables.

Q.8 Solve both questions :[6+8=14]

  1. (a) Identify the following logic functions implemented at F:

    Question Diagram

  2. (b) Implement the following CMOS logics:
    (i) \( \overline{AB(A+B)} \)
    (ii) \( \overline{((CD) + B)A} \)

Q.9 Solve both questions :[8+6=14]

  1. (a) What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.

  2. (b) Find the values of X in the following conversions:
    (i) \( (95.10)_{10} \) to \( (X)_2 \)
    (ii) \( (70)_8 \) to \( (X)_2 \)
    (iii) \( (168.16)_8 \) to \( (X)_{16} \)