Digital Electronics - End Semester Examination - 2023

2023•Semester 2•Civil-CA•End Semester
Bihar Engineering University, Patna
End Semester Examination - 2023

Digital Electronics

Time: 03 HoursCode: 100403Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Answer any seven Question only:[14]

  1. Draw Truth table of JK flip flop.

  2. Convert the Decimal number (108.025) to their binary equivalent.

  3. Draw the truth table and logic circuit of Half-adder.

  4. Write the difference between combinational & Sequential circuit.

  5. Draw timing diagram of SR flip-flop.

  6. Find 2's complement of 1011011.

  7. Number of 2:1 mux requires designing 256:1 mux is

  8. Add hexadecimal number 2ABC & 98F2.

  9. Discuss Universal gates.

  10. What is the use of K-map?

Q.2 Solve this question :[14]

  1. Implement the following function using only NAND gate \( F(A,B,C)=\Sigma m(0,1,2,3,7) \).

Q.3 Solve both questions :[7+7=14]

  1. Realize XNOR logic function using NAND gate only.

  2. Simplify \( Y=ABC+AB\overline{C}+A\overline{B}C \)

Q.4 Solve this question :[14]

  1. A logic circuit has four inputs A,B,C,D and output Y. Y=1 when A & B are both 1, subjected to the condition that C and D are both low or both high. Design the logic circuit.

Q.5 Solve this question :[14]

  1. Explain Master-slave flip flop. What are race around condition?. How it can be circumvented with the help of Master-slave flip flop.

Q.6 Solve both questions :[7+7=14]

  1. Design 8 to 3 line Encoder circuit.

  2. Implement NAND gate using TTL logic family.

Q.7 Solve this question :[14]

  1. Summarize the design procedure for a synchronous sequential circuit.

Q.8 Solve both questions :[7+7=14]

  1. Explain the working of R-2R Ladder DAC.

  2. Design 3-bit binary counter using T flip-flop.

Q.9 Write short notes on the following:[14]

  1. (a) Binary Parallel Adder

  2. (b) Digital IC logic families