Digital Electronics - B.Tech 4th Semester Examination, 2024

2024•Semester 2•Civil-CA•End Semester
Bihar Engineering University, Patna
B.Tech 4th Semester Examination, 2024

Digital Electronics

Time: 03 HoursCode: 100403Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Answer of the following questions (any seven only):[14]

  1. What is the use of K-map?

  2. Discuss Universal gates.

  3. Add hexadecimal number 2ABC & 98F2.

  4. Number of 2:1 mux requires designing 256:1 mux is .........

  5. Find 2's complement of 1011011.

  6. What is the function of a sample-and-hold circuit?

  7. Define term propagation delay.

  8. Define race around condition in JK flip flop.

  9. What is the purpose of expanding memory size?

  10. Differentiate between ROM and RAM.

Q.2 Solve both questions :[14]

  1. Realize XNOR logic function using NAND gate only.

  2. Simplify \( Y = ABC + AB\overline{C} + A\overline{B}C \)

Q.3 Solve this question :[14]

  1. A logic circuit has four inputs A, B, C, D and output Y. Y = 1 when A & B are both 1 subjected to the condition that C and D are both low or both high. Design the logic circuit.

Q.4 Solve both questions :[14]

  1. Design 8 to 3 line Encoder circuit.

  2. Implement NAND gate using TTL logic family.

Q.5 Solve both questions :[14]

  1. Design a parallel-to-serial converter using shift registers and explain its operation.

  2. Compare the characteristics and applications of JK and T flip-flops.

Q.6 Solve both questions :[14]

  1. Explain the working principle of an R-2R ladder DAC with a detailed diagram.

  2. Design a 3-bit flash ADC and explain its working with an example.

Q.7 Solve both questions :[14]

  1. Find the Simplified logical expression for Y.
    \( Y (A, B, C, D, E) = \Sigma m \)(0, 2, 4, 7, 8, 10, 12, 16, 18, 20, 23, 24, 25, 26, 27, 28)

  2. Summarize the design procedure for a synchronous sequential circuit.

Q.8 Solve both questions :[14]

  1. Implement S-R, T, D flip-flops using J-K flip-flop. Also show the implementation with help of State Tables.

  2. Discuss the organization and operation of content-addressable memory (CAM).

Q.9 Write short notes on the following:[14]

  1. (a) Binary Parallel Adder
    (b) Digital IC logic families