Computer Architecture - B.Tech 4th Semester Examination, 2017

2017•Semester 2•Civil-CA•End Semester
Bihar Engineering University, Patna
B.Tech 4th Semester Examination, 2017

Computer Architecture

Time: 3 hoursCode: 051402Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Answer the following questions (any seven):[14]

  1. Write the range of decimal integer can be represented by n-bit 2's complement representation.

  2. Justify the statement "Stack computer consists of an operation code only with no address field".

  3. What do you mean by Arithmetic shift left operation?

  4. What do you mean by locality of reference?

  5. What are the properties of an ideal instruction set computer.

  6. Define the term hardware polling.

  7. What do you mean by data hazards in pipelining?

  8. Explain indirect address mode, and how the effective address in calculated in this case.

  9. Explain the use of subroutine with the help of suitable example.

Q.2 Solve this question :[14]

  1. Why is read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs?

Q.3 Solve this question :[14]

  1. Explain the concept of virtual memory with the help of diagram. Explain how virtual address in mapped to actual physical address.

Q.4 Solve this question :[14]

  1. What is meant by Addressing Mode? Explain at least five different Addressing Modes with an example.

Q.5 Solve this question :[14]

  1. What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?

Q.6 Solve this question :[14]

  1. Explain Von Neumann Architecture. What are its drawbacks?

Q.7 Solve this question :[14]

  1. What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.

Q.8 Solve this question :[14]

  1. Why does I/O interrupt make more efficient use of the CPU? Explain the sequence of operations that take place in an interrupt driven I/O transfer.

Q.9 Solve this question :[14]

  1. How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?