Computer Architecture - B.Tech 4th Semester Exam., 2019

How many \( 128 \times 8 \) bit RAMs are required to design \( 32k \times 32 \) bit RAM?

1. 512
2. 128
3. 1024
4. 32

The sequence of events that happen during a typical fetch operation is

1. PC \( \rightarrow \) MAR \( \rightarrow \) Memory \( \rightarrow \) MDR \( \rightarrow \) IR
2. PC \( \rightarrow \) Memory \( \rightarrow \) MDR \( \rightarrow \) IR
3. PC \( \rightarrow \) Memory \( \rightarrow \) IR
4. PC \( \rightarrow \) MAR \( \rightarrow \) Memory \( \rightarrow \) IR

in case of pipelining processor, loop buffer is

1. very high speed memory maintained by the instruction fetch stage
2. very high speed memory maintained by the instruction decode stage
3. very high speed memory maintained by the instruction execute stage
4. None of the above

The intradata transfer techniques are implemented using

1. serial I/O
2. parallel I/O
3. Both (i) and (ii)
4. Neither (i) nor (ii)

The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is

1. 55 ns
2. 45 ns
3. 90 ns
4. 19 ns

The minimum time delay between the initiations of two independent memory operations is called

1. access time
2. cycle time
3. transfer rate
4. latency time

In case of vectored interrupt, interrupt vector means

1. the branch information from the source which interrupts the system
2. an address that points to a location in memory where the beginning address of the I/O service routine is stored
3. Both (i) and (ii)
4. None of the above

A microprogrammed control unit

1. is faster than a hardwired control unit
2. facilitates easy implementation of new instructions
3. is useful when every small program is to be run
4. usually refers to the control unit of the microprocessor

Relative addressing mode is used to write position independent code because

1. the code in this mode is easy to atomize
2. the code in this mode is easy to relocate in the memory
3. the code in this mode is easy to make resident
4. the code execution faster in this mode

Which of the following holds data and processing instructions temporarily until the CPU needs it?

1. ROM
2. Control unit
3. Main memory
4. Coprocessor chip

How do instruction set, compiler technology, CPU implementation and control, and cache and memory hierarchy affect the CPU performance? Justify the effects in terms of program length, clock rate and effective CPI.

How is virtual memory managed using paging and TLB? Explain with suitable example.

Explain register reference and memory reference instructions in detail with suitable examples.

Draw the block diagram of control unit of basic computer. Explain in detail with control timing diagrams.

Explain one, two and three-address instruction with suitable examples.

Give an integrated diagram, showing the TLB and cache operations for a logical/virtual address generated by a processor.

Explain the daisy chaining mechanism for bus arbitration. Analzye the three bus arbitration methods-daisy chaining, polling and independent requesting with respect to communication reliability in the even of hardware failures.

Give the block diagram of microprogram sequencer for a control memory and explain it properly.

What do you understand by hardwired control? Give various methods to design hardwired control unit. Describe any one with suitable example.

Describe autoincrement and autodecrement addressing modes with proper examples.

What is direct memory access? Explain. Give block diagram of circuitry required for direct memory access.

A digital computer has a common bus system of 16 registers of 32 bits each. The bus is constructed with multiplexers. (i) How many selection inputs are there in each multiplexer? (ii) What size of multiplexers is needed?

When do you say the floating point number is normalized? Explain how floating point representation of number is done. Represent the number (+46.25) as floating point binary number with 32 bits.

What are hazards in pipeline architecture? Explain its type with suitable example.

What is array processor? Explain SIMD array processor with suitable example.

A DMA controller transfers 16-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at the rate of 2400 characters per second. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of DMA transfer?