Computer Organization and Architecture - End Semester Examination - 2023

A pipeline stage

1. Is sequential circuit
2. Is combination circuit
3. Consists of both sequential and combinational circuit
4. None of these

A direct mapped cache memory with n blocks is nothing but which of the following set associative cache memory originations

1. 0-way set associative
2. 1-way set associative
3. 2-way set associative
4. n-way set associative

The performance of a pipelined processor suffers if

1. The pipeline stages have different delays
2. Consecutive instruction are dependent on each other
3. The pipeline stages share hardware resources
4. All of these

A computer with cache access time of 100 ns, a main memory access time of 1000 ns, and a hit ratio of 0.9 produces an average access time of

1. 250 ns
2. 200 ns
3. 190 ns
4. None of these

Which of the following has no practical usage?

1. SISD
2. SIMD
3. MISD
4. MIMD

A micro programmed control unit

1. Is faster than a hardwired control unit
2. Facilitates easy implementation of new instructions
3. Is useful when every small program is to be run
4. Usually refers to the control unit of the microprocessor

In memory- mapped I/O...

1. The I/O devices and the memory share the same address space.
2. The I/O device have a separate address space
3. The memory and I/O device have an associated address space
4. A part of the memory is specifically set aside for the I/O operation

How many \( 128 \times 8 \) bit RAMs are required to design \( 32k \times 32 \) bit RAM?

1. 512
2. 128
3. 1024
4. 32

The stalling of the processor due to the unavailability of the instruction is

1. Control hazard
2. Structural hazard
3. Input hazard
4. None of the above

The addressing mode, where you directly specify the operand value is called as

1. Immediate
2. Direct
3. Definite
4. Relative

What are the hazards in pipeline architecture? Explain its types with suitable example.

What is addressing mode? Why do computers use addressing mode techniques? Explain two modes with example, which do not use address fields.

A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.

How is the virtual address mapped into physical address? What are the different methods of writing into cache?

What are the different types of instruction formats?

Discuss the different mapping techniques used in cache memories and their relative merits and demerits.

Design a 4-bit carry-look ahead adder and explain its operation with an example.

Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.

What is DMA? Describe how DMA is used to transfer data from peripherals.

Differentiate between hardwired and micro programmed control unit. Explain each component of hardwired control unit organization.

What do you mean by asynchronous data transfer? Explain strobe control and hand shaking mechanism.

Show the systematic multiplication process of \( (20) \times (-19) \) using Booth's algorithm.

The stage delays in a four stages pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increases (in percentage) of the pipeline?

Explain IEEE standard for floating point representation with example.