BASIC ELECTRONICS ENGINEERING - B.Tech 3rd Semester Exam., 2020

2020Semester 2Civil-CAEnd Semester
Bihar Engineering University, Patna
B.Tech 3rd Semester Exam., 2020

BASIC ELECTRONICS ENGINEERING

Time: 3 hoursCode: 100303Full Marks: 70

Instructions:

  1. The marks are indicated in the right-hand margin.
  2. There are NINE questions in this paper.
  3. Attempt FIVE questions in all.
  4. Question No. 1 is compulsory.
Q.1 Answer the following questions (any seven):[2×7=14]
  1. Why is negative feedback desired in amplifier application?

  2. Draw the voltage transfer curve of op-amp.

  3. State the Barkhausen's criteria for electronic system to oscillate with feedback.

  4. How is amplifier different from the oscillator?

  5. Why is the reception in the case of amplitude modulation usually noisy?

  6. What is cell splitting and how does it increase the capacity of cellular network?

  7. Justify that BJT is current controlled while FET is voltage-controlled device.

  8. Name the breakdown mechanism in the lightly doped P-N junction diode under reverse biased condition.

  9. Why is Gray code also called as reflected code? Convert \((396)_{10}\) to Gray code.

  10. For the logical circuit shown in the figure, derive the simplified Boolean expression for output Y.

    Question Diagram
Q.2 Solve both questions:[7+7=14]
  1. Draw the waveform of output \(V_{0}\) and explain the operation of circuit with AC source \(V_i\), Resistor R, Parallel diode clippers with bias voltages \(V_{R1}\) and \(V_{R2}\).

    Question Diagram
  2. In the given circuit, calculate the load current \(I_{L}\) and Zener diode current \(I_{Z}\) with 20V source, 1k\(\Omega\) resistor, 5V Zener diode, 1.2k\(\Omega\) Load \(R_L\).

    Question Diagram
Q.3 Solve both questions:[7+7=14]
  1. Calculate the maximum DC voltage and DC current available from a half-wave rectifier. What is the PIV of the diode used in the rectifier?

    Question Diagram
  2. Calculate the value of \(R_{1}\) in the biasing circuit, so that the Q-point is fixed at \(I_{C}=8~mA\) and \(V_{CE}=3~V\) with \(-V_{CC} = -9V\), 250\(\Omega\) collector resistor, 500\(\Omega\) emitter resistor, \(\beta=80\).

    Question Diagram
Q.4 Solve both questions:[7+7=14]
  1. Minimize the given Boolean function F using K map in SOP and implement using NAND gate: \(F(A,B,C,D)=AB\overline{C}D+\overline{A}BCD+\overline{A}\overline{B}\overline{C} \) + \( \overline{A}\overline{B}\overline{D}+A\overline{C}+A\overline{B}C+\overline{B}C\)

  2. The circuit given is the basic application of op-amp to perform the addition operation. Explain the operation of circuit and derive the expression of output voltage.

    Question Diagram
Q.5 Solve both questions:[7+7=14]
  1. Design the voltage follower using op-amp and explain the operation.

  2. Draw the circuit diagram of voltage-shunt feedback amplifier and derive the expression of closed-loop voltage gain.

Q.6 Solve both questions:[7+7=14]
  1. Draw the block diagram of cellular network and briefly explain its operation.

  2. Draw the functional block diagram of AM transmitter and receiver.

Q.7 Solve both questions:[7+7=14]
  1. Design Schmitt trigger using IC 555 timer and explain its operation with the help of functional diagram.

  2. If \(R_{1}=R_{2}=R_{3}=450~k\Omega\) and \(C_{1}=C_{2}=C_{3}=60pF\), determine the frequency of oscillation in phase-shift oscillator. Draw the basic circuit of an R-C phase-shift oscillator and explain its operation.

Q.8 Solve both questions:[7+7=14]
  1. A new clocked X-Y flip-flop is defined with inputs X and Y in addition to the clock input. The flip-flop functions are as follows:
    If XY=00 the flip-flop changes state with each clock pulse.
    If XY=01 the flip-flop state Q becomes 1 with the next clock pulse.
    If XY=10, the flip-flop state Q becomes 0 with the next clock pulse.
    If XY=11, no change of state occurs with the clock pulse.
    Write the truth table and excitation table of X-Y flip-flop. Implement the X-Y flip-flop using a J-K flip-flop.

  2. What is the race around condition in J-K flip-flop? What are the methods to resolve the race around condition in J-K flip-flop? Explain each method with the help of example.

Q.9 Solve both questions:[7+7=14]
  1. What are the problems with normal encoder? How can these problems be solved by the priority decoder? Design 2 to 4 lines priority encoder.

  2. Draw the block diagram of micro-controller and briefly explain each block.